Summary
I build the systems that let hardware teams develop, simulate, verify, and validate silicon earlier and faster: build and release flows, CI and regression infrastructure, verification methodology, developer experience, software and firmware driven RTL simulation, and hardware and software co-design.
Increasingly focused on AI-native engineering: designing context-rich LLM skills, evaluation systems, multi-agent orchestrators, and guarded workflows that automate or substantially augment RTL, DV, and hardware-development work with minimal human supervision. I combine deep ASIC and DV credibility with production-engineering judgment and a shift-left mindset.
Core capabilities
- AI-native hardware engineering: context-rich LLM skills, agentic workflows, multi-agent orchestration, skill and workflow evals, tool integration, human review and failure handling
- Engineering methodology evolution: test-based methodology, to software and firmware driven validation, to CI and build-flow automation, to context-rich, agent-driven execution and continuous evaluation
- ASIC infrastructure and developer experience: build and release flows, CI, regression systems, simulation infrastructure, developer workflows, reproducibility, automation, triage
- Hardware and software co-design: software and firmware driven RTL simulation, early software bring-up, compiler and driver interaction, pre-silicon system validation
- ASIC and accelerator engineering: architecture, RTL, digital and mixed-signal inference hardware, performance, power, memory and dataflow, interfaces, silicon risk
- Verification: verification planning, UVM and SystemVerilog, assertions, coverage, constrained-random testing, formal-verification collaboration, pre-silicon and post-silicon debug
- Programming: Python, SystemVerilog and UVM, C and C++, Tcl
- Tools and environments: Git, Perforce, Jenkins, Buck, Bazel and Blaze, VCS and Verdi, Incisive and Xcelium, Questa, Linux, distributed build and simulation environments
- Interfaces and memory: PCIe, USB, AXI, AHB, and APB, I2C, RISC-V, DDR, GDDR, and HBM
Experience
Meta, Reality Labs, June 2021 to present
ASIC Methodology and Verification Engineer, Austin, TX, Full Remote. Role is largely within the ML accelerator and inference IP team, with AI-native and infrastructure work spanning the wider RL silicon org.
- Design and deploy AI-native engineering workflows using context-rich LLM skills, multi-agent orchestration, evaluation frameworks, and tool-connected flows to automate or substantially augment RTL and DV work.
- Provide agents with project and team context so they can execute multi-step engineering objectives, such as portions of a DV test plan or RTL implementation, with limited human supervision.
- Establish evaluation and review methods for agent-generated engineering work, including quality gates, regression checks, and human review.
- Own and enable engineering infrastructure for complex wearable and smart-glasses silicon programs, across hardware, architecture, design, verification, software, and firmware boundaries.
- Build and evolve ASIC build-flow methodology, CI, regression, simulation, release, and developer-experience systems that make hardware development more reproducible, observable, and scalable.
- Shift validation left by bringing software and firmware behavior into RTL simulation and pre-silicon workflows earlier.
Meta, Datacenter Infrastructure, May 2020 to June 2021
ASIC Engineer, Inference Accelerator. Verified an in-house machine-learning inference accelerator ASIC for Meta datacenter use, and owned verification and sign-off work for a compute-tile subsystem including custom arithmetic units, RISC-V CPUs, fabric interfaces, and local storage.
Mythic, Austin, TX, July 2018 to May 2020
Staff Digital Verification Engineer. Verified a low-power mixed-signal ASIC for neural-network inference using UVM-based randomized testing and software and firmware co-simulation. Developed verification methodology, automation, CI and regression infrastructure, and reusable flows, and helped scale the DV team by about 3 times.
Google, Mountain View, CA, February 2016 to July 2018
Hardware Engineer. Verified machine-learning training and inference ASICs, including Cloud TPU v2 and v3 and Edge TPU projects. Coordinated design and verification work with external IP vendors, contributed RTL for DMA and PCIe, USB, AXI, and I2C interfaces, and owned top-level verification across multiple projects.
NVIDIA, Santa Clara, CA, January 2008 to February 2016
Senior Hardware Engineer. Designed and verified DRAM controllers and page-stream-sorting logic for desktop GPUs, created test plans, evaluated coverage, and led unit-verification efforts across multiple tapeouts.
Education
University of Michigan, Ann Arbor, MI. MSE, Computer Engineering, concentration in Hardware Systems, December 2007. BSE, Computer Engineering, minor in German Studies, April 2006. Eta Kappa Nu.
Publications
- Chico: an on-chip hardware checker for out-of-order cores, MTV 07
- CoSMa: post-silicon verification for cache coherence, ICCD 08
- INFERNO: streamlining verification with inferred semantics, TCCAD 08