About
Hardware engineer and ASIC infrastructure leader, nearly 20 years across GPU, server, edge, and wearable silicon.
At Reality Labs I build the infrastructure, workflows, and AI-native systems that let silicon teams develop and verify hardware faster and earlier: build and release flows, CI and regression, verification methodology, developer experience, and software and firmware driven RTL simulation for shift-left validation.
In the past year, that work moved from single-task LLM assistance to multi-agent RTL and DV workflows with human-on-the-loop review, evaluation, and guardrails, across my team and the wider RL silicon org. Senior technical lead, often leading autonomous pods, not a people manager.
Background in DV and architecture for inference accelerators: Cloud TPU v2 and Edge TPU at Google, mixed-signal compute-in-memory at Mythic, and memory subsystems in four NVIDIA desktop GPU generations, Fermi, Maxwell, Pascal, and Volta, most with first-silicon production.
Experience
From GPUs to ML accelerators to wearable silicon.
Meta, Reality Labs
June 2021 to present, Austin, TX, Full Remote
ASIC Methodology and Verification Engineer
Role is largely within the ML accelerator and inference IP team, with AI-native and infrastructure work spanning the wider RL silicon org. I design and deploy AI-native engineering workflows using context-rich LLM skills, multi-agent orchestration, evaluation frameworks, and tool-connected flows, and I own and enable the engineering infrastructure surrounding complex wearable and smart-glasses silicon programs.
Meta, Datacenter Infrastructure
May 2020 to June 2021
ASIC Engineer, Inference Accelerator
Verified an in-house machine-learning inference accelerator ASIC for Meta datacenter use, including a compute-tile subsystem with custom arithmetic units, RISC-V CPUs, fabric interfaces, and local storage.
Mythic
July 2018 to May 2020, Austin, TX
Staff Digital Verification Engineer
Verified a low-power mixed-signal ASIC for neural-network inference using UVM-based randomized testing and software and firmware co-simulation. Developed verification methodology, automation, CI and regression infrastructure, and reusable flows used across the hardware team.
Google
February 2016 to July 2018, Mountain View, CA
Hardware Engineer
Verified machine-learning training and inference ASICs, including Cloud TPU v2 and v3 and Edge TPU projects. Contributed RTL for DMA and PCIe, USB, AXI, and I2C interfaces, and owned top-level verification across multiple projects.
NVIDIA
January 2008 to February 2016, Santa Clara, CA
Senior Hardware Engineer
Designed and verified DRAM controllers and page-stream-sorting logic for desktop GPUs, and led unit verification efforts across multiple tapeouts, using DDR3 and DDR4, GDDR5, and HBM memory technologies.
University of Michigan
MSE December 2007, BSE April 2006
Computer Engineering, concentration in hardware systems, minor in German Studies, Eta Kappa Nu.